Sigma delta modulators are typically used for analog to digital or digital to analog data conversion. In communications field, sigma delta modulators are typically used in digital radio processor (DRP) transmitter chains for digital to analog data conversion. These DRP transmitters operate in the giga-hertz (GHz) frequency range. At such high frequency of operation and the need for increased bit resolution results in requiring a high number of bits to be processed. As such, the digital sigma delta sigma modulators are embedded in integrated circuits implemented in parallel pipeline stages. A pipeline is a set of data processing elements that are connected in series so that the output of one element is the input to the next element in the chain. Parallel pipelines are implemented to process a number of data bits simultaneously to increase throughput. However, the use of parallel pipeline stages requires additional circuit elements such as delay elements (e.g. buffers or flip-flops) for bits alignment and synchronization. The use of delay elements increases the output latency. It also leads to increased area requirement for embedding the delay elements in the integrated circuit. Further, these delay elements consume power resulting in increased overall power consumption. Yet further, the use of additional circuit elements in the sigma delta modulators introduces noise to the radio frequency (RF) stages of the transmitter chains.
FIG. 1 shows a prior art 1-bit accumulator 100, which is a basic building block of a Multi-stage noising shaping Sigma Delta Modulator (MSDM). Typically, the one-bit accumulator 100 includes a full adder 105 and delay elements 110 and 115. The adder 105 receives a 1-bit data input, D_in, and a 1-bit carry input data, C_in, as shown. The output sum from the adder 105 is fed into the delay element 110 before being fed back to the adder 105. The adder 105 also generates a 1-bit carry out data, C_out, which is fed to the delay element 115. Throughout the disclosure, the 1-bit accumulator 100 is represented by a simplified graphical representation 120 as shown in FIG. 1.
FIG. 2 shows a prior art example of a parallel pipeline two-stage MSDM 200 capable of processing two data bits operating at 2 GHz frequency. Typically, in practice, more than two data bits are processed. The example of FIG. 2 is used as an illustration only. The MSDM 200 includes first stage accumulators 210 and 230 and second stage accumulators 220 and 240. Accordingly, the first stage accumulator 210 and second stage accumulator 220 form a first pipeline and the first stage accumulator 230 and second stage accumulator 240 form a second pipeline. Looking at the first stage, the input data into the MSDM 200 is separated into individual bits such that bit 1 is fed into accumulator 210 via a delay element 205 and bit 2 is fed directly into accumulator 230. The purpose of the delay element 205 is to synchronize the time of bits arrival at accumulators 210 and 230. Looking at the second pipeline, the output sum from accumulator 230 is fed to accumulator 240 via a delay element 235. The output carry bits from accumulators 230 and 240 are fed directly into accumulators 210 and 220, respectively. At the first pipeline, the output sum from accumulator 210 is fed to accumulator 220 via a delay element 215. The output carry bit from accumulator 210 is fed to a combiner 250 via a delay element 245 and the output carry bit from accumulator 220 is also fed to the combiner 250 where the processed bits are combined to provide a final processed output data.
Delay elements 215 and 235 are consequential of concatenating two 1-bit accumulators. These delay elements ensure that bits going into the second stage accumulators are synchronized. In practice, when more bits are processed and the number of stages increases, the number of delay elements needed is correspondingly increased. This contributes to increased latency, power consumption and greater area occupancy in the integrated circuit. Accordingly, there is a need for a multi-stage noise shaping sigma delta modulator that can be synthesized in an integrated circuit to operate at high speed with reduced power consumption, area requirement, noise, and latency.